The present invention relates to flash memory devices and a method of fabricating the same and, more particularly, to flash memory devices and a method of fabricating the same, which can improve the coupling ratio of a cell.
With the high integration of semiconductor substrates, the process of forming isolation layers becomes more complicated. For this reason the isolation layers are formed using a shallow trench isolation (STI) method of forming trenches in a semiconductor substrate and gap-filling the trenches. Meanwhile, there are several methods other than the STI method. The methods can include self-aligned (SA)-STI and self-aligned floating gate (SA-FG) formation methods in which trenches are formed at the same time by etching an exposed semiconductor substrate at a specific depth, while patterning a tunnel insulating layer, a polysilicon layer and a hard mask layer stacked over the semiconductor substrate, and an oxide layer is formed on the entire surface so that the trenches are gap-filled.
In the prior art, the same critical dimension (CD) is applied to the active region and the floating gate, while using the SA-FG formation method. Accordingly, the semiconductor substrate is divided into an active region and a field area, each of which are about half a pattern pitch. In high-integrated devices, it is difficult to gap-fill an excessively small trench area potentially requiring 7 to 8 complicated steps to form the isolation layers.
As the CD of the active region becomes small, there is no method of increasing the size of the floating gate. This poses a significant problem in ensuring the coupling ratio of a cell. However, currently, the thickness level of a dielectric layer having an ONO stacked structure of an oxide layer, a nitride layer and an oxide layer has reached its limit. Accordingly, there is a need for a new method for ensuring the coupling ratio of a cell.